The inventive concepts described herein relate to a method for fabricating a semiconductor device using a hybrid mask pattern.
The integration density of memory devices has recently increased due to the rapid development of miniaturized semiconductor processing technology. Consequently, unit cell area of memory devices has been greatly reduced and operating voltage lowered. For example, in the case of semiconductor elements such as dynamic random access memory (DRAM), along with the increase in degree of integration and the reduction of area occupied by semiconductor elements such as DRAM, it is necessary to maintain or increase capacitance. In order to meet the need of increased capacitance, the aspect ratio of cylindrical type lower electrodes have greatly increased. However, as a result of increased aspect ratio a problem that typically arises is that the cylindrical type lower electrodes fall down or are broken before dielectric is deposited.